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16.5.5 USARTn_STATUS - USART Status Register
Offset
0x010
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8
RXFULL
0
R
RX FIFO Full
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one more
frame in the receive shift register.
7
RXDATAV
0
R
RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
6
TXBL
1
R
TX Buffer Level
Indicates the level of the transmit buffer. If TXBIL is cleared, TXBL is set whenever the transmit buffer is empty, and if TXBIL is set,
TXBL is set whenever the transmit buffer is half-full or empty.
5
TXC
0
R
TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when data is written to the
transmit buffer.
4
TXTRI
0
R
Transmitter Tristated
Set when the transmitter is tristated, and cleared when transmitter output is enabled. If AUTOTRI in USARTn_CTRL is set this bit
is always read as 0.
3
RXBLOCK
0
R
Block Incoming Data
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the
instant the frame has been completely received.
2
MASTER
0
R
SPI Master Mode
Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS command.
1
TXENS
0
R
Transmitter Enable Status
Set when the transmitter is enabled.
0
RXENS
0
R
Receiver Enable Status
Set when the receiver is enabled.
16.5.6 USARTn_CLKDIV - Clock Control Register
Offset
0x014
Reset
Access
Name
Bit Position
2011-04-12 - d0001_Rev1.10
205
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